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dpas Reconfigurable and Adaptive Systems Research
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Contact Info:
Team Leader:
Maya Gokhale
Email: maya@lanl.gov
Phone: 505-665-9095

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Last modified:
27 Jun 2008
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CompilerPublicationsDownloads

Compiler Publications

  • Communications Scheduling for Concurrent Processes on Reconfigurable Computers
  • A Reconfigurable Computing Fabric
  • Comparison of High-Level FPGA Design Tools for a BPSK Signal Detection Application
  • Gamma-Ray Pulsar Detection using Reconfigurable Computing Hardware
  • Evaluation of the Streams-C C-to-FPGA Compiler: An Applications Perspective
  • Stream-Oriented FPGA Computing in the Streams-C High Level Language
  • Automatic Allocation of Arrays to Memories in FPGA Processors With Multiple Memory Banks
  • NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
  • Compiling for Fine-grained FPGA Architectures
  • The Malleable Architecture Generator
  • An overview of the dbC language and its platforms
  • Description of the dbC Napa compiler
  • Description of the dbC Splash compiler
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