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dpas Reconfigurable and Adaptive Systems Research
 RASR
    Evolvable Hardware
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Team Leader:
Maya Gokhale
Email: maya@lanl.gov
Phone: 505-665-9095

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Last modified:
27 Jun 2008
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CompilerPublicationsDownloads

Algorithmic hardware compilers

To make reconfigurable computers accessible to software programmers and embedded systems programmers, we have developed tools to compile high level algorithmic descriptions into hardware. The Streams-C compiler was one of the first efforts to target hardware/software embedded systems using a parallel processing model expressed in the C-language. Streams-C is available in source form for research use (see the Download page). It has been commercialized by Impulse Accelerated Technologies.

To facilitate low level design of datapaths and associated controllers, we have developed the Fabric Generator. This is a Java-based library that facilitates the creation of customized datapaths, especially for application-specific cellular arrays. It includes a DSP-style control structure with definite iteration loops, and additional constructs to allow the fabric cells to synchronize with a microprocessor. This is especially useful for Systems on a Programmable Chip containing configurable logic cells and microprocessors.

We are currently developing a new compiler. The compiler uses the LLVM compiler infrastructure as a front end, and draws on the BYU Sea Cucumber synthesizing compiler for backend code generation.

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