Weighted Order Statistic Classifiers with Large Rank-Order Margin
R. Porter, D. Eads, D. Hush, J. Theiler, submitted for publication, 2003. LA-UR-03-0545

Optimizing Digital Hardware Perceptrons for Multi-Spectral Image Classification
R.Porter et. al., accepted for publication, 2003, LA-UR-03-0546

Evolution on FPGAs for Feature Extraction
Reid Porter, PhD thesis, Queensland University of Technology, 2001, LA-UR-02-3396

Everything on the Chip: A Hardware-Based Self-Contained Spatially-Structured Genetic Algorithm for Signal Processing,
S. Perkins, R. Porter and N. Harvey, ICES2000:  Third International Conference on Evolvable Systems, Edinburgh, Scotland, 17-19 April, 2000.

An Applications Approach to Evolvable Hardware,
R. Porter, K. McCabe and N. Bergmann, The First NASA/DOD Workshop on Evolvable Hardware, Pasadena, California, 19 - 21 July, 1999.

Implementing GA-Accelerators using FPGAs,
R.Porter, Student Workshop in GECCO'99, Orlando, Florida, July 13-17, 1999.

Evolving FPGA Based Cellular Automata,
R. Porter and N. Bergmann, SEAL'98 : Simulated Evolution and Learning, Canberra, 1998.

A Generic Implementation Framework for FPGA Based Stereo Matching,
R. Porter, N. Bergmann, TENCON'97, Brisbane, 2-4 Dec, 1997.